System architects are now compelled to integrate all these design considerations when producing a design that blends diverse hardware components with complex software architecture subject to constraints on the entire system (e.g., response time). Indeed, the sheer size of the design space along with the inter-play of constraints at multiple levels of software and hardware abstractions renders empirical and incremental design processes fairly ineffective. We envision a systematic and hierarchical framework for the configuration, optimization, design and deployment of complex embedded systems.

The central idea is to approach the embedded system design challenge as a configuration problem. More specifically, at the macro level, given a fixed partial hardware platform specification and an abstract software specification, the problem formulation is to decide how to select and specialize the hardware components and select suitable software concretizations so that the complete design satisfies design constraints and optimizes a selected design objective such as runtime, energy usage, cost, weight, and/or size. The objective is to develop a tool that integrates within a modeling eco-system, in which the hardware and software components can be specified, optimized and configured. The tool would be responsible for deriving and solving a discrete optimization based on this specification to produce a complete design that can be subsequently simulated or used to derive an actual embedded system implementation.

At the micro level, our central idea is to develop methods for deterministic and efficient execution of concurrently executing applications on parallel computing hardware i.e., multicore and GPU processors. Multicore is here to stay, it is identified as a key potential technology in IEEE Computer Vision 2022; they have the capability to substantially improve fault-tolerance, performance (latency and throughput) and power/energy efficiency of embedded systems. However, many of the on-chip resources in parallel hardware, such as cores, caches, networks-on-chip and memory controllers are shared resources. Unfortunately, this exposes a well-known limitation of multicores, the “interference” bottleneck. This problem poses a serious threat in safety critical embedded systems since it causes large utilization variations due to vastly different data access behaviors across multiple concurrently executing applications, precludes quality-of-service guarantees, and degrades throughput and energy efficiency. We envision a set of novel static and dynamic isolation and partitioning technologies to efficiently harness the multicore non-determinism challenge.